1. Field of the Invention
The present invention relates to partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistors (FETs) and, more specifically, to embodiments of a PDSOIFET structure with a gate-to-body tunnel current region for threshold voltage (Vt) lowering and a method of forming the PDSOI FET structure.
2. Description of the Related Art
A semiconductor-on-insulator (SOI) field effect transistor (FET) is a FET formed in the semiconductor layer of a semiconductor-on-insulator (SOI) wafer. Shallow trench isolations (STI) structures extend through the semiconductor layer and isolate the SOI FET from other devices within the semiconductor layer. As with any FET, an SOIFET comprises a channel region positioned between source/drain regions and a gate structure positioned above the channel region. However, depending upon the configuration of the source/drain regions as well as the thickness of the semiconductor layer, the channel region of the SOIFET may be fully depleted (FD) or partially depleted (PD). Specifically, in a FDSOIFET, the depletion layer of the channel region between the source/drain regions encompasses the full thickness of the semiconductor layer. In a PDSOIFET, the depletion layer between the source/drain regions is only located in an upper portion of the semiconductor layer near the top surface.
In a PDSOIFET, the non-depleted portion of the channel region that is between the source/drain regions and below the depletion layer is typically referred to as the body of the FET. If this body is not contacted, it is referred to as a floating body. Since the floating body is not contacted (i.e., not biased), its voltage may vary (e.g., as result of leakage currents to Vdd or ground). Variations in the voltage of the floating body will lead to variations in the threshold voltage (Vt) of the PDSOIFET. Furthermore, such threshold voltage variations can differ between PDSOIFETs at different locations within an electronic circuit and can, thereby degrade the performance of the electronic circuit. Performance degradation is particularly notable when some FETs within the electronic circuit require lower threshold voltages than others. For example, in a static random access memory (SRAM) cell within an SRAM array, the pull-down FETs require a lower threshold voltage than the pull-up and pass-gate FETs. Therefore, there is a need in the art for a floating body PDSOIFET structure that provides for threshold voltage (Vt) lowering to, for example, ensure that a FET requiring a lower threshold voltage than other FETs in the same electronic circuit will have a lower threshold voltage.